Level shifter with output spike reduction

ABSTRACT

A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.

This application claims priority under 35 USC 119 to U.S. provisionalapplication No. 61/135,278 filed Jul. 18, 2008 and entitled “Circuitsfor a Charge Pump with Common Mode Tuning Op Amp”, the entire contentsof which are hereby incorporated herein by reference.

BACKGROUND

1. Field

The present disclosure is applicable to electronic integrated circuits(“ICs”), and particularly to level shifter circuits that convert binarysignals from one voltage range to a different voltage range.

2. Related Art

It is usually desirable for an IC to operate from a single voltagesupply. However, many ICs require two or more different voltage suppliesinternally for ideal operation. In such circumstances a binary-levelsignal that operates satisfactorily within the bounds of a first supplyoften needs to be conditioned so that it is capable of controllingcircuits that operate across a different, typically wider, voltagerange. Ideally, circuits are available that accept a logic level inputsignal to control one or more outputs that each range from the mostpositive voltage of a first, higher supply voltage to the lowest (ormost negative) voltage of a second, lower supply voltage. In this paper,such circuits are referred to as “level shifters”. The logic levelsignal range need not be identical to either the higher or the lowersupply voltage.

FIG. 1 illustrates an example of a level shifter that responds to alogic level input to control a circuit operating over a wider voltagerange than that of the logic supply. The circuit operating over a widervoltage range is a relatively simple RF switch. A differential outputlevel shifter 800 accepts a “Select A/B” input signal 102 that operatesbetween logic+ and logic−. Both level shifter outputs switch between thepositive supply, VDD 104, and the negative supply, VSS 106, depending onthe voltage of the input 102. If the input 102 is high then OUT 108 willbe driven to approximately VDD, while OUTX 110 will be driven toapproximately VSS.

The voltages of the logic supply, and of VDD 104 and VSS 106, depend onthe requirements of the circuit in which the level shifter operates. VDDand VSS supplies are often symmetric, having the same magnitude voltage.The exemplary embodiment described in the most detail herein is suitablefor symmetric positive and negative supplies, but is also suitable forasymmetric supplies. As one example, logic+ and VDD 106 may both have avalue of approximately 2.4V with respect to circuit common, which inturn may be approximately equal in potential to an RF reference voltage“ground” 140. VSS 106 may be −3.4V with respect to ground 112.

In other circuits the supply values may vary widely. As a firstrepresentative alternative, VDD may be +10V, logic+ +3V, logic− 0V, andVSS −10V. As a second representative alternative, VDD may be +6V, VSSmay be −5V, and logic+ may be 0V while logic− is −5V. In a thirdalternative, VDD may be 2.4V, logic+ may be 2.4V, logic− may be 0 orcommon, and VSS may be −2.4V. The input control voltage range need notextend to either VDD or VSS. Indeed, though it is typically so, 0V orthe “common” voltage disposed between VDD and VSS need not constituteeither logic+ or logic−.

In the exemplary circuit of FIG. 1 the outputs OUT 108 and OUTX 110control an SPDT (single pole double throw) RF switch to connect anantenna 114 to either an RF input A 116, or to an RF transmit signal B118. When Select A/B 102 is high (or, more generally, “true”), the levelshifter output OUT 108 is driven to about VDD, turning on FETs M₁ 120and M₂ 122. The level shifter inverted output OUTX 110 is concurrentlydriven to VSS, turning off FETs M₃ 124 and M₄ 126. Consequently, theantenna 114 is coupled via FET M₂ 122 to input A 116 of a low noiseamplifier (LNA) 128, which provides an amplified signal to RF Rcv 130which is coupled to further receive processing circuits (not shown).

An RF signal intended for transmission may be provided to RF input 132of a power amplifier 134, the output of which is matched to theimpedance of the antenna 114 by a matching network 136. The matchingnetwork typically includes a blocking capacitor or other mechanism suchthat the RF transmit signal B 118 has a large amplitude RF signal with amean voltage of zero volts. The RF Xmt input 132 should be quiescentwhen Select A/B 102 is true. In this “A” selection condition, FET M₃ 124is off, while FET M₁ 120 shunts any residual signal present at B 118 toground 112, thus minimizing interference with the extremely small RFreceive signal picked up by the antenna 114.

When Select A/B 102 is false, OUT 108 is driven to VSS and OUTX 110 isdriven to VDD. This causes FETs M₃ 124 and M₄ 126 to be turned on, andFETs M₁ 120 and M₂ 122 to be turned off. Accordingly, the RF transmitsignal A 118 is no longer shunted to ground by M₁ 120, but instead iscoupled to the antenna 114. The sensitive input to the LNA 128 isprotected by M₂ 122 having a high impedance, plus M₄ 126 shunting anyleakage signal to ground 112. Gate resistors (not shown) in series withthe gate of each of M1-M4, in conjunction with parasitic drain-gate andgate-source capacitances Cdg and Cgs, protect the FETs from sufferingexcess voltages from gate to drain or source (Vgs and Vgd) because ofthe high frequency of the zero-average RF signal at B 118.

FIG. 1 illustrates an exemplary use of a level shifter to provide drivecontrol to an RF signal switch circuit. The voltages VDD and VSS may beadjusted to the requirements of the FET switches, which often operate atmuch higher voltages than those employed for select signal Select A/B102. The FETs of the RF SPDT switch may be high voltage devices, or maybe low voltage devices arranged in a “stacked” or multiple-gateconfiguration that increases the overall voltage withstand capability ofthe switch. Of course, though FIG. 1 illustrates only one type of usefor level shifter circuits such as level shifter 800, level shifters areemployed in myriads of different types of circuits. Level shifters arethus highly useful for a wide range of purposes.

A method and apparatus having improved features for level shifting aredescribed herein. The maximum operating voltage of a level shifterdepends in part on the characteristics of the semiconductor process bywhich it is fabricated. However, circuit switching details may causevoltages to appear across devices, such as FETs, that have a transientvalue that is greater than the static voltages of the circuit. Suchexcessive voltages, even though transient, may eventually cause thelevel shifter circuit to fail even if they are too small to causeapparent harm for some time.

Among other useful features, the method and apparatus described hereininclude features that avoid such excessive transient voltages acrosssemiconductor devices of a level shifter. This enables a givensemiconductor process to control higher voltage and power, resulting inmore cost-effective and reliable level shifters. Various aspects of themethod and apparatus described herein will be seen to provide furtheradvantages, as well.

SUMMARY

An improved level shifting method and apparatus is described forgenerating a control output that has a significantly wider voltage rangethan the voltage range over which an input control signal operates. Manylevel shifter topologies are possible, some examples of which are setforth in U.S. Pat. No. 6,804,502 entitled “Switch Circuit and Method ofSwitching Radio Frequency Signals” issued Oct. 12, 2004 to Burgener, etal., the entire contents of which are hereby incorporated herein byreference.

One embodiment is a method of creating a final output signal from alevel shifter circuit that substantially approaches a maximum voltageVDD in a first static state and a minimum voltage VSS in an oppositesecond static state, the state controlled by an input control signal tothe level shifter within an input control voltage range that issubstantially smaller than, and distinct from, the range from VDD toVSS. The method includes generating the final output signal from a finaloutput drive block and generating, for each final output drive block ofthe level shifter, upper and lower source supply signals fromcorresponding upper and lower source supply drivers. Each upper sourcesupply signal is “at a rail” approximating VDD in one static state andis “at common” approximating an intermediate value COM in the oppositestatic state, and each lower source supply signal is “at a rail”approximating VSS in one static state and “at common” approximating COMin the opposite static state, such that in each of the opposite staticstates one of the source supply signals for a particular final outputdriver is “at a rail” and the other of the source supply signals is “atcommon”. In response to each change from one state to the opposite stateinitiated by a change in the input control signal, the method furtherincludes preventing the source supply signal that is “at common” frombeginning to transition away from that condition until after anotherdrive signal has completed a significant portion of a transition from“at a rail” toward its “at common” value.

The method of the foregoing embodiment may include generating, undercontrol of a single control signal to a level shifter circuit, both afirst differential final output signal from a first final output driveblock and a second differential final output from a second final outputdrive block, the first and second final output signals inverted withrespect to each other such that in one static state the first finaloutput approaches VDD and the second output approaches VSS, and in theopposite state the second output approaches VDD and the first outputapproaches VSS. The method includes providing a corresponding upper andlower source supply signal pair to each of the final output blocks suchthat in each static state one of each pair of source supply signals is“at common” and the other source supply signal of the pair is “at arail”. The method may further include, in response to a change from onestate to the opposite state initiated by the single control signal,preventing the source supply of one pair that is “at common” frombeginning to transition to “at a rail” until after a source supplysignal of the other pair has transitioned substantially from “at a rail”toward “at common”. In response to the same change of state, the methodmay alternatively prevent the source supply of each pair that is “atcommon” from beginning to transition to “at a rail” until after theother source supply signal of such pair has transitioned substantiallyfrom “at a rail” toward “at common”.

In some embodiments the level shifter may have two stages including afront end level shifter stage that produces differential intermediatelevel shifted outputs inverted with respect to each other fromintermediate output drivers under control of the same input controlsignal, plus high and low intermediate source supply signals for each ofthe intermediate output drivers. In that case, the method may furtherinclude coupling VSS to all intermediate output drivers and allintermediate source supply drivers of such a front end level shifterstage via a resistor larger than 1000 ohms. The method may also includedisposing a capacitance between the high and low intermediate sourcesupply signals for each intermediate output driver.

Another embodiment is a level shifter having at least one final outputranging from about a maximum voltage VDD of a positive supply withrespect to a common voltage in a first static state to about a minimumvoltage VSS of a negative supply with respect to common in a secondstatic state, either state selectable by an input voltage value withinan input voltage range much less than the range VSS to VDD. Each finaloutput driver stage is supplied by a corresponding high-level sourcedrive circuit having an output “at a rail” and approximating VDD in onestate and “at common” approximating common in the opposite state, and bya corresponding low-level source drive circuit having an output “atcommon” approximating common in one state and “at a rail” approximatingVSS in the opposite state, such that in each static state one of thesource drive outputs is “at common” and the other source drive output is“at a rail”, such final output drive circuit thereby providing a finaloutput at approximately VDD in one state and VSS in the opposite state.The level shifter further includes “away from common” transition delaycircuitry configured to delay a transition by a source drive output from“at common” toward a rail until a different source drive output hassignificantly transitioned from “at a rail” toward common.

The level shifter may be a differential-output level shifter includingcircuitry to produce final outputs inverted from each other, anon-inverted final output being approximately VSS in a first state andapproximately VDD in an opposite second state, and an inverted finaloutput being approximately VDD in the first state and approximately VSSin the opposite second state. In that case the “away from common”transition delay circuitry may preclude transmission of a changingcontrol signal to a source drive circuit for the non-inverted finaloutput driver having output “at common” until after a different sourcedrive output for the inverted final output driver has significantlytransitioned from “at a rail” toward common. Initiation of alltransitions of source drive outputs from “at common” toward “at a rail”may be similarly precluded until a source drive output from a relativelyinverted final output driver has significantly transitioned from “at arail” toward common.

The “away from common” delay circuitry may alternatively delayinitiation of transitions by a source drive output for a particularfinal output driver from “at common” until after a source drive outputfor the same particular final output driver has significantly begun totransition from “at a rail” toward common.

Any such level shifter may include two level shifting stages, eachindependently generating a final output ranging from VDD to VSS basedonly on one or more input signals each limited to a range substantiallysmaller than VDD to VSS. In particular, the input signal ranges may belimited to the range VDD to common and/or the range common to VSS,exclusive of signals ranging from VDD to VSS. Any such level shifter mayadditionally include a resistor within an order of magnitude of 10 kohms in series between a supply source and all circuits of a levelshifter stage coupled to such supply source. Any such level shifter mayinclude circuitry that clamps each high-side and low-side controlsignals for a supply source driver at a level causing the supply sourcedriver to output common, and to unclamp such control signals only afteranother supply source driver output significantly transitions towardcommon from “at a rail”. In particular, any such level shifter mayconcurrently clamp such control signals and decouple the clamped controlsignal from a signal source by means of a clamped-output transmissiongate.

Embodiments of the level shifting method or apparatus may employ anycombination of individual features of any described embodiment, insofaras such combination of features is practical and is not expresslydisavowed within this paper.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will be more readily understood byreference to the following figures, in which like reference numbers anddesignations indicate like elements.

FIG. 1 is a simplified schematic diagram of a level shifter controllingan RF switching circuit.

FIG. 2 illustrates the circuit that is represented by inverter symbols.

FIG. 3 is a simplified schematic diagram of a level shifter stage.

FIG. 4 illustrates a transmission gate plus clamp circuit block forhigh-side signals.

FIG. 5 illustrates a transmission gate plus clamp circuit block forlow-side signals.

FIG. 6 schematically illustrates a single-stage level shifter circuitcontrolled by a high-side control signal between ground and VDD.

FIG. 7 schematically illustrates a single-stage level shifter circuitcontrolled by a low-side control signal between VSS and ground.

FIG. 8 schematically represents a two-stage differential output levelshifter with output block drive supply differential limiting.

FIG. 9 schematically represents a two-stage single-ended output levelshifter with output block drive supply differential limiting.

DETAILED DESCRIPTION

The level shifting method and apparatus described herein areparticularly suited to avoiding a transient appearance of excessivedifferential voltage between drive signals coupled to an output driveblock (or intermediate output drive block) of an integrated circuitlevel shifter.

FIG. 2 illustrates the transistor configuration represented by invertersymbols 200 throughout this paper. The inverter symbols include an inputIN 202 on the side opposite the “bubble”, and an output OUT 204 at theend of the bubble. Input IN 202 is coupled to the gates of both a Pchannel FET MP 206 and an N channel FET MN 208. The drains of these twoFETs are both coupled to OUT 204. The source of MP 206 is coupled to apositive supply connection “V+_(SRC)” 210, represented schematically bya plus sign “+”, while the source of MN 208 is coupled to a negativesupply connection “V−_(SRC)” 212, represented by a minus sign “−”.

Ideally, the threshold voltages of the FETs are controlled to be greaterthan half of the expected maximum voltage difference between V+_(SRC)210 and V−_(SRC) 212, such that when IN 202 is rising, MP 206 will turnoff before MN 208 begins to turn on, and vice versa. However, in theexemplary process the threshold voltage are only about IV, while theexpected voltage difference between V+_(SRC) 210 and V−_(SRC) 212 istypically 2.4 V. As such, there is a finite amount of time when bothdevices in an inverter 200 are “on”, causing simultaneous conduction or“shoot-through” current. However, unlike clocked circuits, levelshifters switch a control signal which changes relatively infrequently,so a modest amount of transitional electrical noise does notsignificantly add to average emissions. For frequent signal changes, orwhen input transitions are slow, the supplies V+_(SRC) 210 and V−_(SRC)212 are limited, typically by means of current limit circuits.

The devices for each inverter 200 are selected for the desired outputdrive capacity. For balanced output drive, the MP 206 may need to havesome combination of greater wider and/or shorter length compared to theMN 208, due to the typically lower conductance of a given size of Pchannel FET versus an equal sized N channel FET.

Unless otherwise noted, the inverters represented in subsequent figuresby inverter symbols of type 200 may be assumed to have N and P FETs thatare differently sized to be comparably conductive. The size of theinverter symbols 200 roughly indicates the size of the devices in therepresented inverter. Small, medium and large inverter symbols 200 areemployed. In an exemplary silicon-on-sapphire process employed by theinventor, all FETs in inverter blocks 200 may be assumed to have Vth ofabout 1 V (−1 V for P FETs). Small inverter blocks may be assumed toindicate an N FET 208 having a channel of 2 microns width and 0.8 micronlength, and a P FET 206 having a channel of 3 micron width and 0.5micron length. Medium size inverters represent an N FET having a channel4 microns wide and 0.8 microns long, and a P FET with channel 6 micronswide, 0.5 microns long. The large inverter symbols 200 represent an NFET of channel width 20 microns and length 0.8 microns, and a P FET alsoof width also 20 microns but of length 0.5 microns. The skilled personwill have no trouble selecting suitable FET sizes for varying processesand circuit requirements.

FIG. 3 is a simplified schematic of a basic single-stage level shifter.In overview, inputs to a high-side inverter 302 and a low-side inverter308 control the source voltages for an output inverter 314. VDD 104 iscoupled to the V+_(SRC) connection of a first inverter block 302 whoseV−_(SRC) connection is coupled to a common voltage 304 which is oftenapproximately midway between VDD 104 and VSS 106. The input 306 toinverter 302 operates typically switches between the levels of VDD 104and common voltage 304, though devices may be fabricated to acceptinputs over other ranges. A second inverter block 308 has the V+_(SRC)input coupled to the common voltage 304 and the V−_(SRC) coupled to VSS106, so that its input 310 typically, though not necessarily, accepts acontrol input that switches between approximately VSS 106 and common304.

The output 312 of inverter 302 switches between about common 304 and VDD104, and is provided to the V+_(SRC) connection of a third, largerinverter block 314 whose V−_(SRC) connection is coupled to the output316 of the inverter 308, which switches between about VSS 106 and common304. Accordingly, when a suitable logic low level (about common 304) isapplied to input 306, and a different suitable logic low level (aboutVSS 106) is applied to input 310, outputs 312 and 316 go to VDD andcommon, respectively. Thus, inverter 314 has only a single supplyvoltage (VDD—common) disposed across its source connections. When inputs306 and 310 are switched to suitable logic low levels of about commonand VSS, respectively, the outputs 312 and 316 go to common voltage andVSS, respectively. Thus, output inverter 314 again has only one supplyvoltage (common—VSS) disposed across its source connections.

Thus, the V+_(SRC) connection 312 and V−_(SRC) connection 316 of theoutput inverter 314 switches between VDD and common, respectively, forsuitable logic low levels on inputs 306 and 310, and common a VSS,respectively, for suitable logic high levels on inputs 306 and 310.Because the input of the output inverter 314 is coupled to common 304,its output 318 goes to about VDD in the logic low input condition, andto about VSS in the logic high condition. Output 318 is the primaryoutput of this level shifter stage.

In some exemplary embodiments of level shifters, the FETs in inverterblock 314 have the same breakdown voltage as do those in inverters 302and 308, and both are close to the greater of the first supply(VDD—common) or the second supply (common—VSS). Under such circumstancesit is important that outputs 312 and 316 are never at VDD and VSS,respectively, and indeed it is important that the voltage differenceacross the outputs not exceed the greater of the two supply voltagemagnitudes at any time either the P FET or the N FET of output inverterblock 314 is conducting. Such overvoltage conditions may be avoided bythe principles illustrated in the circuits of FIGS. 4-9.

FIGS. 4 and 5 are signal transmit blocks that include a transmissiongate and a clamp to common. Signal Transmit H 400 of FIG. 4 is intendedfor operation with a “high” side signal between VDD and common. Thetransmission gate consisting of P FET 402 and N FET 404 couples a signalbetween input I 406 and output O 408 when the control signals _X 410 andX 412 are logic low (common) and high (VDD) respectively. The signal iswithin a suitable voltage range, which in the exemplary embodiment isthe same as the range of the control inputs 410 and 412, i.e., betweencommon and VDD. When the control signals _410 and X 412 are inverted tologic high (VDD) and low (common) respectively, the signal at I 406 isblocked, and the output O 408 is clamped down to common by N FET 414.

Signal Transmit L 500 of FIG. 5 is intended for “low” side operationbetween common and VSS. The transmission gate consisting of N FET 502and P FET 504 couples a signal between input I 506 and output O 508 whenthe control signals _X 510 and X 512 are logic low (VSS) and high(common) respectively. The signal is within a suitable voltage range,which in the exemplary embodiment is the same as the range of thecontrol inputs 510 and 512, i.e., between VSS and common. When thecontrol signals _X 510 and X 512 are inverted to logic high (common) andlow (VSS) respectively, the signal at I 506 is blocked, and the output O508 is clamped up to common by P FET 514.

FIGS. 6 and 7 are both schematic diagrams of single stage differentialoutput level shifters. The level shifter 600 of FIG. 6 operates with a“high side” logic control input at IN_G2VD 602, i.e., between common(low) and VDD (high). The level shifter 700 of FIG. 7 operates with a“low side” logic control input at IN_VS2G 702, i.e., between VSS (low)and common (high).

The level shifter 600 includes a non-inverting output OUT_VS2VD 604 thatrises from VSS to VDD when the input IN_G2VD rises from common to VDD,and an inverted output OUT_VD2VS 606 that falls from VDD to VSS inresponse to the same input change. The two outputs are generated by twoinverter trios configured similarly as the high-side inverter 302,low-side inverter 308 and output inverter 314 of FIG. 3. High-sideinverter 608, low-side inverter 610 and output inverter 612 generate thenon-inverting output OUT_VS2VD 604. This output is renderednon-inverting from the input by the additional high-side inverter 614that inverts IN_G2VD for the input to inverter 608. High-side inverter616, low-side inverter 618 and output inverter 620 generate invertingoutput OUT_VD2VS, which, as in FIG. 3, is inverting with respect to theinput.

The input to low-side inverter 610 is provided by the inverting outputOUT_VD2VS 606. However, that output signal ranges from VSS to VDD, so itis limited to the proper input range (VSS to common) by N FETs 622 and624. When the output OUT_VD2VS 606 is VDD, N FET 622 couples the inputof 610 to common 304, and when the output is VSS, N FET 624 couples theinput of 610 to VSS. Similarly, the input to low-side inverter 618 isprovided by the non-inverting output OUT_VS2VD 604, which is limited tothe low-side input range by N FETs 626 and 628.

In addition to the extra inverting stage 614 and the signal limitingFETs 622-624 and 626-628, each half of level shifter 600 differs fromthe circuit of FIG. 3 by virtue of an impedance Zs 630 in the connectionto source supply VSS 106. Zs 630 serves to limit the value of thelow-side supply during transitions from one state to another. Becausethere is little DC current flow, it has no impact on steady-statevoltages. In conjunction with capacitors 632 and 634 (typically about0.5 pF each), Zs 630 limits the transient voltage swings that wouldotherwise occur across the source supplies of the output inverters 612and 620, respectively. The high-side inverters 608 and 616 are directlycontrolled by IN_G2VD 602; hence outputs O_G2VD 636 and O_VD2G 638 willbegin to change first. Capacitor 634 causes the sink of inverter 620 totrack its source, O_VD2G 638, causing output OUT_VD2VS 606 to rise. Inturn, that causes inverter 610 to drive toward VSS, which reinforces themovement toward VSS by O_VS2G that was previously caused by capacitor632 as driven by inverter 608. In the same manner, capacitor 632 enablesinverter 612 to almost immediately switch toward VSS in response to afalling input at IN_G2VD 602. That in turn causes inverter 618 toreinforce the rise toward ground of O_G2VS 640 that was previouslycaused by capacitor 634 driven by inverter 616.

Zs 630 may serve a plurality of purposes. It may facilitate an abilityof capacitors 632 and 634 to maintain the source voltage across outputinverters 612 and 620 reasonably constant during the switching sequence.It also slows switching speed. In exemplary embodiments Zs is simply aresistor of 5 k to 20 k ohms, but may have a resistance within an orderof magnitude of 10,000 ohms. Moreover, Zs may have an inductivecomponent, or even be primarily inductive, in which case the impedancemagnitude should be determined at a transition frequency Ft that is1/Ts, where Ts is the transition time from an input transition at, e.g.,IN_G2VD 602, to O_VS2G 642. Ts may alternatively be calculated as thetime between other suitable voltage transitions. The magnitude of theimpedance Zs should be greater than 1000 ohms at Ft, or may be limitedto being within an order of magnitude, or alternatively within a factorof 4, of 10,000 ohms at Ft. Generally, it is preferable for it to besubstantially larger than Rds(on) of the inverters to which it iscoupled (inverters 610, 618 in FIG. 6, and 704, 708 in FIG. 7). Zs may,in fact, be an active FET device, with or without a second cascodedevice, configured to operate substantially as a limited current sourceduring transitions. Zs 630 is particularly useful when the VDD and VSSsupplies (with respect to common) are asymmetric, i.e., have differentmagnitudes, in which case Zs should be disposed in series with thesupply that is of larger magnitude. VDD and VSS are asymmetric in anexemplary embodiment: VSS is about −3.4 V, while VDD is about +2.4 V,both with respect to common. Accordingly, in such embodiment Zs 630 isdisposed in series with VSS.

The single stage differential output level shifter 700 of FIG. 7operates quite similarly as level shifter 600. However, input IN_VS2G702 directly drives low-side inverters 704 and 708, the latter via extralow-side inverter 710. Thus, low side output O_G2VS 712 will switchfirst, closely followed (due to extra inverter 710) by low side outputO_VS2G 714. Capacitors 716 and 718 (e.g., about 0.5 pF) will hold thesource voltage substantially constant across the output inverters 720and 722, respectively. This in turn permits the output inverters toswitch the outputs OUT_VS2VD 724 and OUT_VD2VS 726. Those outputvoltages create the input voltages to high-side inverters 728 and 730,respectively, after limitation to high-side input range by P FET pairs732, 734 and 736, 738, respectively. The switching of the high-sideinverters 730 and 732 finally reinforces the voltage of outputs O_VD2G740 and O_G2VD 742, which were initially driven only via the capacitors716 and 718. As in the level shifter 600, Zs 744 (5 k to 20 k ohms,primarily resistive, in exemplary embodiments) may be disposed in serieswith a supply, particularly when VDD and VSS are asymmetric with respectto common. Zs 744 may serve, for example, to facilitate the ability ofthe capacitors 716 and 718 to maintain constant source voltage for theoutput inverters during switching, particularly when the VDD and VSSsupplies are asymmetric. Zs 744 may take on any value as described abovefor Zs 630, and may be replaced by a current limiting circuit.

FIG. 8 schematically illustrates a two-stage differential output levelshifter 800. The first stage 802 is a single stage differential outputlevel shifter having outputs as indicated in the level shifters 600 and700 of FIGS. 6 and 7. However, because input 804 is presumed to accepthigh-side control levels, level shifter 802 employs the switching logicof the level shifter 600. The level-shifted outputs of the first stage802 (OUT_VS2VD and OUT_VD2VS) are used only internally. Only thehigh-side and low-side outputs, including the inverted outputs O_VD2Gand O_G2VS, respectively, and the non-inverted outputs O_G2VD andO_VS2G, respectively, are used. These signals are coupled to a secondstage of level shifter 800 via signal transmit blocks. The high-sideoutputs are coupled via Signal Transmit H blocks 806 and 808, then viahigh-side inverters 810 and 812, to produce high side signals Sa 814 andSd 816. These signals are again inverted by higher power inverters 818and 820 to produce VDa 822 and VDb 824, which are V+_(SRC) connectionsfor the highest power output inverters 826 and 828, respectively. Theoutputs of those inverters 826 and 828 are the final level shifteddifferential outputs OUT 830 and OUTX 832 of the two stage level shifter800. Similarly, the low-side outputs are coupled to the second stage viaSignal Transmit L blocks 834 and 836, and then via low-side inverters838 and 840 to establish signals Sb 842 and Sc 844. Larger low-sideinverters 846 and 848 produce the low-side non-inverted and invertedoutputs VSa 850 and VSb 852, respectively. VSa 850 and VSb 852 are theV−_(SRC) connections for the output inverters 826 and 828, respectively.

Either the V+_(SRC) or the V−_(SRC) connection of an output inverter isat common 304 in every static state. If such connection at commonvoltage moves toward its particular supply rail (VDD for V+_(SRC), VSSfor V−_(SRC)) faster than the opposite source connection moves towardcommon, then the net voltage across the output inverter will increaseabove its static value. This can impair reliability if the FETs areoperating near their voltage withstand capacity. To avoid such transientvoltage spikes it is desired to ensure that whichever source supply(V+_(SRC) or V−_(SRC)) will be moving toward common voltage will beforced to substantially begin its transition before the opposite sourceis permitted to begin transitioning. This is accomplished in the levelshifter 800 by means of the Signal Transmit blocks 806, 808 and 834,836.

When IN 804 is logic high, VDa 822 is at VDD, VSa 850 at common, VDb 824at common and VSb 852 is at VSS. When IN 804 transitions to logic low,all of these voltages will change, but the transitions of VSa 850 andVDb 824 are delayed. They will change in response to the signal fromSignal Transmit L block 834 and Signal Transmit H block 808,respectively. However, signals VSb 852 (VSS) on X and Sc 844 (common) on_X initially disable Signal Transmit L block 834, while signals VDa 822(VDD) on X and Sa 814 (common) initially disable Signal Transmit H block808. VSb 852 and Sc 844 are permitted to change by Signal Transmit Lblock 836, which is initially enabled by VSa 846 (common) on X and Sb842 (VDD) on _X.

When IN 804 is logic low, VDa 822 is at common, VSa 850 at VSS, VDb 824at VDD and VSb 852 is at common. When IN 804 transitions to logic low,the transitions of VDa 822 and VSb 852 are delayed by the initialcondition of Signal Transmit blocks 806 and 836. These Signal Transmitblocks will not be enabled to transmit the new signal from the firststage 802 until VDb 824 and Sd 816, as well as VSa 846 and Sb 842, havesubstantially transitioned. In all cases, suitable transition thresholdvoltages should be selected to ensure that racing cannot permit voltagespikes across the source voltages of the output inverters 826 and 828.

In level shifter 800, initially disabled Signal Transmit blocks for oneside of the level shifter (either the non-inverted OUT side, or theopposing OUTX side) are enabled by the transition of an output an on theopposite side. These signals are not available in single-ended (onesided) level shifters, so an alternative circuit is illustrated for suchlevel shifters in FIG. 9.

A logic input 902 arbitrarily selected to accept inputs between VDD andcommon controls the two stage single-ended level shifter 900 of FIG. 9.The first stage (or front end) is a differential level shifter 904,which may be implemented identically as the level shifter 600 of FIG. 6,or in any other manner that will provide a high-side non-inverted outputO_G2VD between common and VDD, and a low-side non-inverted output O_VS2Gbetween VSS and common. Of course, additional inverters in both sidesaffect only the polarity of the net output OUT 906 from the large outputinverter 908. The small inverters 910 and 912 produce inverted signalsSa 914 and Sb 916, which are inverted by medium inverters 918 and 920 toproduce higher power non-inverted signals VDa 922 and VSa 924, which inturn are V+_(SRC) and V−_(SRC) for the output inverter 908.

Due to the lack of the opposite or differential “side” in a single-endedlevel shifter, one solution is to employ two additional single-stagelevel shifters 926 and 928. The level shifter 926 accepts a high-sideinput control from VDa 922 and thus may be implemented like levelshifter 500 of FIG. 5, while the level shifter 928 accepts a low-sideinput control from VSa 924 and thus may be implemented like levelshifter 600 of FIG. 6. The low-side outputs of level shifter 926,non-inverting output O_VS2G 930 and inverting output O_G2VS 932 arecoupled respectively to X and _X of low-side Signal Transmit L block934. The high-side outputs of level shifter 928, non-inverting O_G2VD936 and inverting O_VD2G 938 are coupled respectively to X and _X ofSignal Transmit H block 940. Thereby, when VDa 922 is at common, it isprevented from switching toward VDD until after a rising VSa enablesSignal Transmit H block 940 via level shifter 928; and conversely, whenVSa 924 is at common, it is prevented from switching toward VSS untilafter a falling VDa 922 enables Signal Transmit L block 934 via levelshifter 926. With proper attention to threshold voltages, level shifter900 may be even more resistant to excess voltage spikes across itsoutput inverter 908 than is level shifter 800, but significantadditional circuitry is used to ensure suitable timing.

Level shifter input voltage ranges are typically between VDD and common,or between common and VSS, but the level shifters can readily bemodified to accept control input over a nearly arbitrary input voltagerange. Input circuitry of level shifter 600 of FIG. 6 accepts controlinput voltages on the high side (VDD to common), while input circuitryof level shifter 700 of FIG. 7 accepts control input voltages on the lowside (common to VSS). In view of such alternative input ranges, incombination with input range limiting circuitry (e.g., such asrepresented by FETs 622 and 624 of FIG. 6) and standard engineeringknowledge, a skilled person will readily be able to implementembodiments of any level shifter described herein to accept inputswithin another input voltage range. Such input voltage range can be madenearly arbitrary by use of range limiting circuitry, plus amplifyingcircuitry if needed. Thus, although a level shifter by definitioncontrols an output over a different output voltage range than the inputvoltage range, no particular restriction on the relationship betweeninput and output voltage ranges is necessary.

Although exemplary embodiments are shown, there are many ways to achievesubstantially the same result. In particular, the Signal Transmit blocksin FIGS. 8 and 9 may be replaced by any suitable logic function thatachieves substantially the same effect. Different level shifter circuitsmay be used in place of level shifter stages 802, 902, 926 and 928, andthe inverter blocks may be implemented differently.

Conclusion

The foregoing description illustrates exemplary implementations, andnovel features, of a level shifter with output spike reduction, and of amethod of shifting voltage while avoiding output drive spikes. Theskilled person will understand that various omissions, substitutions,and changes in the form and details of each of the methods and apparatusillustrated may be made without departing from the scope of suchapparatus or method. Because it is impractical to list all embodimentsexplicitly, it should be understood that each practical combination offeatures set forth above (or conveyed by the figures) that is suitablefor embodying one of the apparatus or methods constitutes a distinctalternative embodiment of such apparatus or method. Moreover, eachpractical combination of equivalents of such apparatus or methodalternatives also constitutes an alternative embodiment of the subjectapparatus or method. Therefore, the scope of the presented methods andapparatus should be determined only by reference to the claims that areappended, as they may be amended during pendency of any application forpatent. The scope is not limited by features illustrated in theexemplary embodiments set forth herein for the purpose of illustratinginventive concepts, except insofar as such limitation is incorporated ina particular appended claim.

The circuits illustrated and described herein are only exemplary, andshould be interpreted as equally describing such alternatives as may bereasonably seen to be analogous by a person of skill in the art, whetherby present knowledge common to such skilled persons, or in the future inview of unforeseen but readily-applied alternatives then known to suchskilled persons.

All variations coming within the meaning and range of equivalency of thevarious claim elements are embraced within the scope of thecorresponding claim. Each claim set forth below is intended to encompassany system, apparatus or method that differs only insubstantially fromthe literal language of such claim, but only if such system, apparatusor method is not an embodiment of the prior art. To this end, eachelement described in each claim should be construed as broadly aspossible, and should be understood to encompass any equivalent to suchelement insofar as possible, except that any construction encompassingthe prior art is an unintended and overbroad construction.

What is claimed is:
 1. A level shifter apparatus having at least onelevel-shifted final output ranging from about a positive supply railvoltage VDD in a first state to about a negative supply rail voltage VSSin a second state, either of the two states adapted to be selected basedon value of an input control signal operating within a rangesubstantially different from the range between the negative supply railvoltage VSS and the positive supply rail voltage VDD, the level shiftercomprising: a) a first inverting circuit and a second inverting circuitconfigured to output a first inverter output voltage and a secondinverter output voltage, respectively, to a first final output circuit,the first final output circuit configured to produce a level-shiftedfinal output based on the first inverter output voltage and the secondinverter output voltage, wherein: i) the first inverter output voltageis within a range from about a common voltage to about the positivesupply rail voltage VDD, ii) the second inverter output voltage iswithin a range from about the common voltage to about the negativesupply rail voltage VSS, and iii) in either of the first and secondstates of the level-shifted final output, one of the inverter outputvoltages is either at about the negative supply rail voltage VSS or atabout the positive supply rail voltage VDD and the other inverter outputvoltage is at about the common voltage; and b) a first transitioncontrol circuitry and a second transition control circuitry connectedwith the first inverting circuit and the second inverting circuit,respectively, each of the transition control circuitries configured todelay a transition of a corresponding inverter output voltage fromaround the common voltage toward either about the negative supply railvoltage VSS or about the positive supply rail voltage VDD until theother inverter output voltage has significantly transitioned from eitherabout the negative supply rail voltage VSS or about the positive supplyrail voltage VDD toward the common voltage.
 2. The level shifter ofclaim 1, further comprising a second final output circuit for producinga level-shifted final output inverted with respect to the level-shiftedfinal output of the first final output circuit, wherein: a) the secondfinal output circuit is coupled to a third inverter output voltage via athird inverting circuit and to a fourth inverter output voltage via afourth inverting circuit, b) the third inverter output voltage is withina range from about the common voltage to about the positive supply railvoltage VDD, and c) the fourth inverter output voltage is within a rangefrom about the common voltage to about the negative supply rail voltageVSS.
 3. The level shifter of claim 2, further comprising a thirdtransition control circuitry and a fourth transition control circuitryconnected with the third inverting circuit and the fourth invertingcircuit, respectively, each of the transition control circuitriesconfigured to delay, after a state change initiated by a change in thevalue of the input control signal, initiation of transitions of acorresponding inverter output voltage from about the common voltagetoward either about the positive supply rail voltage VDD or about thenegative supply rail voltage VSS until the other inverter output voltagehas significantly transitioned from either about the positive supplyrail voltage VDD or about the negative supply rail voltage VSS towardthe common voltage.
 4. The level shifter of claim 3, wherein the firstand second inverter output voltages are coupled to the first finaloutput circuit and the third and fourth inverter output voltages arecoupled to the second final output circuit, and wherein the inverteroutput voltages associated with the transition from either about thenegative supply rail voltage VSS or about the positive supply railvoltage VDD toward the common voltage are coupled to one of the firstand second final output circuits while the inverter output voltagesassociated with the delayed transition are coupled to the other finaloutput circuit.
 5. The level shifter of claim 3, wherein the first andsecond inverter output voltages are coupled to the first final outputcircuit and the third and fourth inverter output voltages are coupled tothe second final output circuit, and wherein one inverter output voltageassociated with the transition from either about the negative supplyrail voltage VSS or about the positive supply rail voltage VDD towardthe common voltage is coupled to one of the first and second finaloutput circuits while another inverter output voltage associated withthe delayed transition is coupled to the same final output circuit. 6.The level shifter of claim 1, wherein the first and second inverteroutput voltages are coupled to the first final output circuit and thethird and fourth inverter output voltages are coupled to the secondfinal output circuit, and wherein one inverter output voltage associatedwith the transition from either about the negative supply rail voltageVSS or about the positive supply rail voltage VDD toward the commonvoltage is coupled to one of the first and second final output circuitwhile another inverter output voltage associated with the delayedtransition is coupled to the same final output circuit.
 7. The levelshifter of claim 1, wherein a change in the value of the input controlsignal results in i) a state change in the level-shifted output voltageand ii) initiation of transitions in each of the first and secondinverter output voltages.
 8. A circuital arrangement having a finaloutput voltage ranging from about a positive supply rail voltage VDD ina first state to about a negative supply rail voltage VSS in a secondstate, either of the two states adapted to be selected based on value ofan input control signal operating within a range substantially differentfrom the range between the negative supply rail voltage VSS and thepositive supply rail voltage VDD, the circuital arrangement comprising:a) a first stage comprising a first level shifter and a second levelshifter, each level shifter comprising the level shifter apparatus ofclaim 1, wherein each level shifter comprises two inverting circuitsconfigured to provide a first intermediate voltage that is within arange from about a common voltage to about the positive supply railvoltage VDD and a second intermediate voltage that is within a rangefrom about the common voltage to about the negative supply rail voltageVSS; b) a second stage configured to produce the final output voltagebased on the first and second intermediate voltages from each of thefirst and second level shifters; and c) a non-parasitic capacitancedisposed between each inverting circuit in the two inverting circuits ineach level shifter.
 9. The circuital arrangement of claim 8, whereineach of the first and second transition control circuitries comprises atransmission gate and a clamping circuit both controlled by outputs ofthe second stage to interrupt and clamp one of the first and secondintermediate voltages from each of the first and second level shiftersto the common voltage and transmit the other intermediate voltage fromeach of the first and second level shifters.
 10. A circuital arrangementhaving a final output voltage ranging from about a positive supply railvoltage VDD in a first state to about a negative supply rail voltage VSSin a second state, either of the two states adapted to be selected basedon value of an input control signal operating within a rangesubstantially different from the range between the negative supply railvoltage VSS and the positive supply rail voltage VDD, the circuitalarrangement comprising: a) a first stage comprising a first levelshifter and a second level shifter, each level shifter comprising thelevel shifter apparatus of claim 1, wherein each level shifter comprisestwo inverting circuits configured to provide a first intermediatevoltage that is within a range from about a common voltage to about thepositive supply rail voltage VDD and a second intermediate voltage thatis within a range from about the common voltage to about the negativesupply rail voltage VSS; b) a second stage configured to produce thefinal output voltage based on the first and second intermediate voltagesfrom each of the first and second level shifters; and c) a supplyimpedance Zs disposed such that coupling of any of the first and secondintermediate voltages to a selected supply that is either the positivesupply rail voltage VDD or the negative supply rail voltage VSS iscoupled to such selected supply via series connection with Zs.
 11. Thelevel shifter of claim 10, further comprising a non-parasiticcapacitance disposed between each inverting circuit in the two invertingcircuits in each level shifter.
 12. A method of developing, in a levelshifter circuit, at least one output signal that substantiallyapproaches an upper supply rail voltage VDD in a first state andsubstantially approaches a lower supply rail voltage VSS in a secondstate, either of the two states adapted to be selected based on value ofan input control signal to the level shifter that falls suitably withinan input control signal range that is substantially smaller than therange from the upper supply rail voltage VDD to the lower supply railvoltage VSS, the method comprising the steps of: a) applying the inputcontrol signal to a first inverting block to generate a first inverteroutput voltage and applying the input control signal to a secondinverting block to generate a second inverter output voltage, wherein:i) the first inverter output voltage is within a range from about acommon voltage to about the upper supply rail voltage VDD, ii) thesecond inverter output voltage is within a range from about the commonvoltage to about the lower supply rail voltage VSS, and iii) in eitherof the first and second states of the at least one output signal, one ofthe inverter output voltages is either at about the lower supply railvoltage VSS or at about the upper supply rail voltage VDD and the otherinverter output voltage is at about the common voltage; b) applying thefirst and second inverter output voltages to a first output block togenerate a first output signal among the at least one output signal; andc) during each transition of the at least one output signal between thefirst and second states initiated by a change in the input controlsignal, delaying initiation of a transition by the inverter outputvoltage that is at about the common voltage until after the otherinverter output voltage that is either at about the upper supply railvoltage VDD or about the lower supply rail voltage VSS has significantlytransitioned toward the common voltage.
 13. The method of claim 12,further comprising: applying the input control signal to a thirdinverting block to generate a third inverter output voltage and applyingthe input control signal to a fourth inverting block to generate afourth inverter output voltage, wherein: i) the third inverter outputvoltage is within a range from about the common voltage to about theupper supply rail voltage VDD, ii) the fourth inverter output voltage iswithin a range from about the common voltage to about the lower supplyrail voltage VSS, and iii) in either of the first and second states ofthe at least one output signal, one of the third and the fourth inverteroutput voltage is either at about the lower supply rail voltage VSS orat about the upper supply rail voltage VDD and the other inverter outputvoltage is at about the common voltage; applying the third and fourthinverter output voltages to a second output block to generate a secondoutput signal among the at least one output signal, wherein the secondoutput signal is inverted with respect to the first output signal,wherein: i) the third inverter output voltage is inverted with respectto the first inverter output voltage, and ii) the fourth inverter outputvoltage is inverted with respect to the second inverter output voltage.14. The method of claim 13, further comprising preventing, for each ofthe first, second, third, and fourth inverter output voltages that is atabout the common voltage, initiation of a transition toward either aboutthe lower supply rail voltage VSS or about the upper supply rail voltageVDD until after the inverter output voltages have completed asignificant portion of a transition from either about the lower supplyrail voltage VSS or about the upper supply rail voltage VDD toward thecommon voltage.
 15. The method of claim 13, further comprisingpreventing initiation of transitions of the inverter output voltagesfrom the common voltage toward either about the lower supply railvoltage VSS or about the upper supply rail voltage VDD until after theother output voltages have transitioned substantially from either aboutthe lower supply rail voltage VSS or about the upper supply rail voltageVDD toward the common voltage, wherein the inverter output voltagesassociated with the transitions from the common voltage toward eitherabout the lower supply rail voltage VSS or about the upper supply railvoltage VDD and the inverter output voltages associated with thetransitions from either about the lower supply rail voltage VSS or aboutthe upper supply rail voltage VDD toward the common voltage are coupledto different output blocks.
 16. The method of claim 13, furthercomprising preventing initiation of transitions of the inverter outputvoltages away from the common voltage toward either about the lowersupply rail voltage VSS or about the upper supply rail voltage VDD untilafter the other inverter output voltages have transitioned substantiallyfrom either about the lower supply rail voltage VSS or about the uppersupply rail voltage VDD toward the common voltage, wherein the inverteroutput voltages associated with the transitions from the common voltagetoward either about the lower supply rail voltage VSS or about the uppersupply rail voltage VDD and the inverter output voltages associated withthe transitions from either about the lower supply rail voltage VSS orabout the upper supply rail voltage VDD toward the common voltage arecoupled to the same output block.
 17. The method of claim 12, whereinthe level shifter circuit comprises a first stage and a second stage,wherein the first stage produces two pairs of intermediate source supplysignals, one of the two pairs consisting of a first intermediate voltageat about the common voltage in the first state and at about the uppersupply rail voltage VDD in the second state and a second intermediatevoltage at about the lower supply rail voltage VSS in the first stateand at about the common voltage in the second state, the other of thetwo pairs consisting of a first intermediate voltage at about the uppersupply rail voltage VDD in the first state and at about the commonvoltage in the second state and a second intermediate voltage at aboutthe common voltage in the first state and at about the lower supply railvoltage VSS in the second state.
 18. The method of claim 17, furthercomprising disposing a non-parasitic capacitor coupled to the first andsecond intermediate voltages of each pair of such supply signals. 19.The method of claim 17, further comprising coupling a selected supply,either the upper supply rail voltage VDD or the lower supply railvoltage VSS, to any intermediate voltage of the first stage only via aseries impedance Zs common to all such couplings to the selected supply.20. The method of claim 19, further comprising disposing a non-parasiticcapacitor coupled to the first and second intermediate voltages of eachpair of such supply signals.
 21. The method of claim 17, furthercomprising delaying initiation of a transition by the inverter outputvoltage that is at the common voltage by interrupting one of the firstand second intermediate voltages from the first stage at about thecommon voltage and clamping such intermediate voltage to about thecommon voltage until the one of the first and second intermediatevoltages from the first stage is unclamped by the other intermediatevoltages significantly transitioning from either about the lower supplyrail voltage VSS or about the upper supply rail voltage VDD toward thecommon voltage.